Don’t beat yourself up if don’t get it perfect the first time. For the last 14 years, first silicon success rates have not improved. The expected number of tape-outs is still around 2.
I analyzed the results from the 2012 and 2018 Wilson Research Functional Verification Study to see if anything has changed in the last decade and a half with regards to ASIC respins. Unfortunately, it appears that the introduction of advanced verification methodologies such as UVM and Formal Verification have not affected first silicon success in any meaningful way. From 2004 to 2018 the expected number of tape-outs have hovered around 2 across the industry. The first silicon success rate has hovered around 31% except for 2018 where it sank a little to 26%. Interestingly, about 25% of all projects needed more than 2 tape-outs before succeeding.
Most projects get it right in two attempts.
Take-aways for engineers
Don’t beat yourself up, if you don’t get it right the first time. Few projects do. On the other hand, if you need 3 tape-outs to get it right, then you aren’t doing as well as your peers. A third tape-out can either come from a bad fix or from a bug that hid behind another bug, so do you best to make both the first and the second tape-out a success. Ask yourself whether you have the required verification quality to ensure that no bugs are big enough for other bugs to hide behind.
Take-aways for managers
Plan on having two tape-outs. There are two common ways to run these and one backup way which some times comes in handy.
If you have a relatively small chip or low confidence in a successful tape-out and 5-6 months of slack in your required time-to-market, then a multi-purpose wafer (MPW) shuttle makes the most economic sense as a MPW shuttle is 10% of the full tape-out price.
If you have a large chip that can’t fit in a MPW shuttle or if you have a no slack in your required time-to-market, that is, the lost revenue from delaying a product launch by 3 months would vastly exceed the tape-out cost, then you should go for a full maskset tape-out and follow up with a metal-only respin.
A metal-only respin has about half the turnaround time as a full mask tape-out since the foundry can process the first half of the fabrication steps from the first tape-out in advance of receiving new masks for the metal layers. A two layer metal change costs about 20% of a full tape-out. You should budget at least 3 months of calendar time to complete a metal-only spin with the time spent evenly between your end and your foundry. A metal-only respin plan requires high confidence in product quality, an experienced physical design team and ample spare or gate-array cells in the floor plan.
A multi-layer maskset (MLM) tape-out is the middle ground between MPW and full maskset. MLM costs A40% of the full maskset tape-out price. It is only really useful when you have low confidence in the product quality, but you can’t wait for an MPW shuttle.
References
- https://semiengineering.com/reduction-in-first-silicon-success/
- https://blogs.mentor.com/verificationhorizons/blog/2019/03/13/part-12-the-2018-wilson-research-group-functional-verification-study/
- https://blogs.mentor.com/verificationhorizons/blog/2013/09/08/part-12-the-2012-wilson-research-group-functional-verification-study/
- https://anysilicon.com/understanding-maskset-type-mpw-mlm-mlr-single-maskset/
- http://europractice-ic.com/mpw-prototyping/general/mlm/